The present invention relates to electronic semiconductor devices having electrical interconnection structures on a substrate and, more particularly, to a method of forming these interconnection structures.
The continued tendency to reduce the geometry and to increase the speed of operation of integrated circuits requires the use of conductors with high conductivity to reduce the cross-sections of the conductive tracks, and the use of dielectrics with low dielectric constants to improve the insulation between adjacent conductive tracks. The most usual method of forming interconnections up to now provides for the formation of a dielectric layer having openings for contact with an underlying layer, the deposition of a layer of metal, typically aluminum, on the dielectric layer, and selective etching of the metal layer by photolithographic techniques to form the necessary interconnection elements.
This method has various disadvantages. These disadvantages include a poor ability to cover stepped structures so that the conductive tracks tend to become thinner on the walls of the openings, poor dimensional control when interconnection elements are defined by wet chemical etching, and other problems with dry etching when the nature of the metal permits it. Aluminium can easily be etched dry but copper or gold cannot. Moreover, with this method, to produce a dielectric layer for covering the interconnection elements, which has a flat surface, it is necessary to use planarizing techniques, for example, chemical-mechanical polishing (CMP), which further complicates the production process and may introduce defects and contamination.
Various alternative methods have been proposed for overcoming the limitations of this known technique. Among these are the known methods which provide for the formation of interconnection elements in a dielectric layer by the hollowing-out of thin channels, the filling of the channels with a metal and the planarization of the surface. This technique is similar to the old technique for decorating metal surfaces known by the name of xe2x80x9cdamascenexe2x80x9d and is defined by the same name in this application to the technology of semiconductor devices.
The single damascene technique produces conductive openings or vias through a dielectric layer while maintaining optimal planarity. By applying the same technique twice (a double damascene technique), it is possible to produce complete interconnections formed by conductive vias through a dielectric layer and interconnection elements formed on the dielectric layer.
With this technique, it is possible to use metals such as copper, which have better conductivity than aluminium. Copper is used predominantly for interconnections according to the conventional technique. Interconnection tracks of smaller cross-section can therefore be produced. However, this technique uses conventional dielectrics and does not permit the production of devices with improved performance with regard to the insulation of the conductive tracks from the semiconductor substrate, or of the tracks from one another.
In view of the foregoing background, an object of the present invention is to provide a method of forming semiconductor devices with high-conductivity interconnections and with insulators having low dielectric constants.